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Sidense Corp., founded in 2004, is a leading developer of silicon-proven, embedded non-volatile memory (NVM) intellectual property (IP). Sidense`s patented 1T-Fuse™-based one-transistor one-time programmable (1T-OTP) memory enables a wide range of electronic products that are built with complex System-on-Chip (SoC) semiconductors. End-market products include home entertainment consumer products, cellular telephones and other mobile communications devices, configurable processors, RFID, medical, industrial, automotive and a host of others. Semiconductor and systems companies integrate Sidense 1T-OTP IP macros into their SoC designs, saving time and money and allowing them to focus on the core competencies that differentiate their products. Sidense provides memory IP that is difficult and uneconomical for the device makers to try to create on their own. Important requirements of Sidense customers include the need to incorporate NVM that can be manufactured on a standard-logic CMOS process with no additional masks or process steps, is field-programmable, has a very small footprint, very fast read access times, is extremely difficult to reverse engineer, and has very low operating and standby power consumption. Sidense is the only supplier of antifuse 1T-OTP IP that can meet all of these demanding requirements at the leading semiconductor foundries from 180nm to 20nm, with development underway at smaller geometries.
Oski`s unique formal verification services deliver peak sign-off confidence earlier in the development cycle by diving deep into design behavior to track down the most complex corner-case bugs. Our approach exhaustively proves the absence of bugs and brings a higher level of productivity to our clients, as compared with traditional simulation and formal verification approaches. Since 2005, Oski has focused on developing comprehensive formal verification methodologies to identify and sign-off high-risk blocks, achieve system-level architecture sign-off, and quickly resolve post-silicon bugs. Oski has built the largest team of formal verification experts in the world. Our founder and Chief Oski, Vigyan Singhal, did his PhD thesis at UC Berkeley in formal methods of verification. Vigyan later developed Cadence`s first-generation formal verification tool, and was the founder of Jasper Design Automation, which was later acquired by Cadence. The company is headquartered in San Jose, CA with a design center in Gurugram, India.
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